Best Practices for HPC Software Developers Webinar Series

The HPC Best Practices (HPC-BP) webinars address issues faced by developers of computational science and engineering (CSE) software on high-performance computers (HPC).


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Published December 21, 2018

Webinars are scheduled on roughly a monthly basis and are available live and then archived for future reference. The event web site provides details about the webinar series, including announcements of upcoming webinars, a mailing list to receive announcements, and archival information for the entire series.

Webinars are free and open to the public, but advance registration is required (individually, for each session).

Next webinar: Quantitatively Assessing Performance Portability with Roofline

Date and Time: Wednesday, January 23, 2018, 1:00-2:00 pm ET

Presenters: John Pennycook (Intel), Charlene Yang (LBNL) and Jack Deslippe (LBNL)


Wouldn't it be great if we could port a code to a new high-performance architecture without substantially changing the code yet achieving a similar level of performance as hand-optimized code? This webinar will frame the discussion around ‘performance portability’, why it is important and desirable, and how to quantitatively measure it. The webinar will start with a background check on how the concept of performance portability came about and past attempts to define it and quantify it. Then we will introduce a simple yet powerful metric and an empirical methodology to quantitatively assess a code’s performance portability across multiple platforms. The methodology uses the Roofline performance model to measure an ‘architectural efficiency’ term in the metric proposed by Pennycook et al. We will dive into a few nuances of this methodology, for example, how and why empirical ceilings should be used for performance bounds, how to accurately account for complex instructions such as divides, how to model strided memory accesses, and how to select the appropriate Roofline ceilings and application performance points to make sure that the performance portability analysis is not erroneously skewed. We will also show some results of measuring performance portability using the aforementioned metric and methodology on two modern architectures, Intel Xeon Phi and NVIDIA V100 GPUs.

More info and registration link:

Past Webinars